At modem age, the integration level of integrated circuit (IC) is rising so that the improvement of IC fabrication technique is becoming significant. Nowadays, a dynamic random access memory (DRAM) is the most common component employed in a very-large-scale integrated (VLSI) circuit. For a DRAM cell composed of a transistor and a capacitor, the surface area of the capacitor has the indication of the storage capacity of DRAM.
Normally, the capacitance of the DRAM can be increased by increasing the surface area of the capacitor. However, even though the capacitance of the capacitor is increased, the integration level will be lowered.
In the current technology of fabricating the capacitor adopted in DRAM, two most widely adopted capacitors in a DRAM cell are a deep trench capacitor and a stack capacitor because they can increase the capacitance of capacitor but the integration level will not be affected. The deep trench capacitor which is fabricated by the trench isolation technique is the most popular capacitor used in a DRAM cell. Nevertheless, some defects still exist in the technology of fabricating deep trench capacitor and the performance of DRAM is restricted.
Please refer to FIG. 1 which shows the patterns of a patterned mask used for fabricating the deep trench capacitor. Conventionally, a patterned photo mask is employed to transfer the pattern to the surface of silicon wafer for forming the opening of the deep trench capacitor.
Please refer to FIG. 2(a) which is the perspective view of the deep trench which is formed by photolithography using the pattern shown in FIG. 1 and then performing an etching process. Normally, the area of the bottom and side walls of the deep trench indicates the effective area of the deep trench capacitor. However, as the integration level of DRAM is rising the dimension is minimized, and the opening of the deep trench capacitor transferred from the patterned mask is inevitably getting small as well. Thus, the effective area of the deep trench capacitor is reduced. That causes a decrement in the capacitance of the capacitor so that the DRAM cell using deep trench capacitor can not work properly. Therefore, several negative influences will occur, for instance, the data retention time of DRAM will become too short to retain the data.
While the opening of the deep trench capacitor is reduced, the opening of the deep trench capacitor formed by transferring the pattern shown in FIG. 1 to the surface of the substrate is shown in FIG. 2(b). It is obvious that as shown in FIG. 2(b), the so-called corner rounding effect is generated, wherein the four corners of the pattern shown in FIG. 2(b) are getting round because of the optical proximity effect (OPE), thereby resulting in a reduced effective area. Conventionally, a solution of the OPE is to apply an optical proximity correction (OPC) program to correct the pattern (the pattern after correction is shown in FIG. 2(c)). However, the OPC program is very complicated, and it is not an efficient way to solve the problem of OPE at the present time.